1. Field of the Invention
The present invention relates generally to a method for logic design of an integrated circuit (IC), more particularly, to a method for estimating the wiring line capacitances on a single chip IC.
2. Description of the Related Art
In fabrication of a logic IC such as a microprocessor, the logic design comes first, followed by the layout design based thereon. In the logic design, the working relationship between the parts of a system is analyzed in detail in terms of the symbolic logic without primary regard for hardware, for example, distribution of wiring lines.
In recent years, logic IC's have been put into practical use in a variety of fields, such as signal processing, electronic control in automobiles, electronically controlled toys, and digital watches, due to the increasingly greater capabilities of logic IC's. For example, so-called custom large-scale integrated circuits (LSI's), such as LSI's manufactured under a building block method and gate array LSI's manufactured under a masterslice method, are being widely marketed. Competition, of course, demands that any new logic IC product be marketed as speedily as possible. This is particularly true with custom LSI's.
In the logic design of logic IC products, it is important to know the lengths of the wiring lines distributed on the related single chip IC. This is because each wiring line necessarily has its own capacitance, i.e., wiring line capacitance, which is, in general, substantially proportional to the length thereof. The wiring line capacitance is a major factor affecting the operation speed of the logic circuit, since it also acts as a load, i.e., load capacitance, for logic circuit driver elements. Accordingly, it is preferable that the lengths of the wiring lines be measured with a high degree of accuracy at the logic design stage to enable the best logic design. As commonly known, the load capacitance, i.e., the length of a wiring line, causes a signal delay--one of the most important parameters when arranging logic gates during the logic design of an IC.
However, it is impossible to measure the length of each wiring line accurately in the logic design stage, because the actual lengths of the wiring lines cannot be correctly determined until the layout design of the logic IC is completed. Thus, it is only possible to estimate the lengths of the wiring lines during the logic design stage. Such estimation is relatively easy for small scale IC's, but is not so easy for large-scale IC's.
Prior art methods of estimation were only able to estimate lengths to inch units and even this was difficult, as clarified hereinafter. Therefore, the lengths of the wiring lines could not be gauged with a high accuracy. This often made reevaluation of the logic design necessary after a trial layout design, thus increasing the time for producing the IC products.